1. Field of the Invention
The present invention relates generally to dynamic semiconductor memory devices, and more particularly, to a semiconductor memory device having a reduced soft error rate.
2. Description of the Background Art
FIG. 1 is a diagram showing a structure of a main portion of a conventional dynamic random access memory (referred to as DRAM hereinafter).
In FIG. 1, a plurality of bit line pairs BL and BL are arranged intersecting with a plurality of word lines WL. Memory cells MC are respectively connected to
intersections of the bit lines BL or BL and the word lines WL. Each of the memory cells MC comprises a transfer gate TG comprising an N channel MOS transistor (metal oxide semiconductor) transistor and a capacitance Cs storing "H" or "L" level information. In addition, dummy word lines DWL0 and DWL1 are arranged intersecting with the bit line pairs BL and BL. Dummy cells DC0 are respectively provided at intersections of the dummy word line DWL0 and the bit lines BL, and dummy cells DC1 are respectively provided at intersections of the dummy word line DWL1 and the bit lines BL. The dummy cells DC0 and DC1 respectively hold an intermediate potential Vcc/2 between a power-supply potential Vcc and a ground potential.
Additionally, sense amplifiers SA are respectively connected between the bit line pairs BL and BL. The plurality of word lines WL and the dummy word lines DWL0 and DWL1 are connected to a row decoder 101. The bit line pairs BL and BL are respectively connected to a data input/output line pair I/O and IO through sets of transfer gates Q1 and Q2 each comprising an N channel MOS transistor. The transfer gates Q1 and Q2 have their gates connected to a column decoder 102.
At the time of data reading, a single word line WL is selected by the row decoder 101, so that a potential thereon is raised to an "H" level. Consequently, data in the memory cell MC connected to the word line WL is read out onto the bit line BL or BL. For example, when the data is read out onto the bit line BL, a potential on the dummy word line DWL1 is raised to the "H" level, so that a potential of the dummy cell DC1 is read out onto the bit line BL. Consequently, the potential on the bit line BL becomes a reference potential Vref. On the other hand, a potential on the bit line BL becomes slightly higher or lower than the reference potential Vref. Thereafter, a potential difference between the bit line pair BL and BL is amplified by the sense amplifier SA. Any one set of the transfer gates Ql and Q2 is turned on by the column decoder 102, so that the data on the bit line pair BL and BL connected thereto is read out onto the data input/output line pair I/O and IO.
Let's consider a potential which appears on each bit line pair BL and BL at the time of data reading.
As shown in FIG. 2, it is assumed that a capacitance C.sub.1 exists between each of the bit lines BL and BL and a ground potential (fixed potential) through a substrate, and a capacitance C.sub.2 between bit lines exists between the adjacent bit lines BL and BL. In addition, it is assumed that a cell capacitance of the memory cell MC is Cs.
Charges stored in the memory cell MC are Cs.multidot.Vcc (writing of Vcc) when "H" level data is stored while being 0 (writing of 0V) when "L" level data is stored. In addition, charges of Cs Vcc/2 (writing of Vcc/2) are respectively stored in the dummy cells DC0 and DC1. Assuming that the bit line pair BL and BL is precharged at Vcc/2 before a reading operation, charges on the bit lines BL and BL are respectively C.sub.1 Vcc/2.
In FIG. 2, if and when data is read out onto a bit line BL1 from the memory cell MC and a potential is read out onto a bit line BL1 from the dummy cell DC, for example, a potential V.sub.BL1 on the bit line BL1 and a potential V.sub.BL1 on the bit line BL1 are respectively found from the following equations: ##EQU1## (+: at the time of writing of Vcc, -: at the time of writing of 0V) ##EQU2## Where V.sub.BL0 denotes a potential on a bit line BL0, and V.sub.BL2 denotes a potential on a bit line BL2. Let's consider a case in which the "H" data is read out onto the bit lines BL0, BL1 and BL2. In this case, the following relation is satisfied: EQU V.sub.BL0 .perspectiveto.V.sub.BL1 .perspectiveto.V.sub.BL2, V.sub.BL0 .perspectiveto.V.sub.BL1 .perspectiveto.V.sub.BL2
When this relation is substituted in the equations (1) and (2), a potential difference .DELTA.V.sub.BL1 (=V.sub.BL1 -V.sub.BL1) between the bit lines BL1 and BL1 is represented by the following equation: ##EQU3##
When integration density of a memory device is increased and a pitch between bit lines is decreased, the capacitance C.sub.2 between bit lines is increased, so that the denominator in the equation (3) becomes large. Consequently, the potential difference between the bit line pair BL and BL at the time of reading is decreased due to noises of capacitive coupling between the adjacent bit lines, so that a read margin is decreased. As a result, a malfunction of the sense amplifier occurs, so that a soft error rate is increased, for example.
A twisted bit line technique for decreasing noises of capacitive coupling between bit lines by a different method from that in the present invention has been proposed in an article entitled "A Twisted Bit Line Technique for Multi-Mb DRAMS", 1988 IEEE International Solid-State Circuits Conference, DIGEST OF TECHNICAL PAPERS, pp. 238-239.